Errata
Page 19
change
There are also DevKitM variants which differ in a few pin positions. All of the diagrams in this book use the C3 so make sure the development board you use has the same pin arrangement.
to
There are also DevKitM variants which differ in a few pin positions. All of the diagrams in this book use the ESP32 and ESP32 S3 C development boards so make sure the development board you use has the same pin arrangement.
Page 210
change
To try either version of the program you need an H‑bridge connected so that GPIO 15 is A, GPIO 16 is B, GPIO 17 is A- and GPIO 18 is B-.
To
To try either version of the program you need an H‑bridge connected so that GPIO 16 is A, GPIO 17 is B, GPIO 18 is A- and GPIO 19 is B-.
Page 234
change
spi=SPI(1,sck=Pin(14),miso=Pin(12),mosi=Pin(13))
spi.init(baudrate=500_000, bits=8, polarity=0, phase=0,
firstbit=SPI.MSB)
CS = Pin(15, Pin.OUT)
CS.on()
To
spi_bus_config_t busConfig = {
.sclk_io_num = 14,
.mosi_io_num = 13,
.miso_io_num = 12,
.quadwp_io_num = -1,
.quadhd_io_num = -1,
};
spi_bus_initialize(SPI2_HOST, &busConfig, SPI_DMA_DISABLED);
spi_device_interface_config_t masterConfig = {
.command_bits = 0,
.address_bits = 0,
.dummy_bits = 0,
.mode = 0,
.queue_size = 10,
.clock_speed_hz = 500000,
.spics_io_num = 15,
};
spi_device_handle_t SPI = NULL;
spi_bus_add_device(SPI2_HOST, &masterConfig, &SPI);
Page 272
Change
|
ESP32 |
HTU21 |
|---|---|
|
SDA GPIO18 |
SDA/DA |
|
SCK GPIO17 |
SCL/CL |
|
3.3v |
VCC/VIN/+ |
|
GND |
GND/- |
To
|
ESP32 |
HTU21 |
|---|---|
|
SDA GPIO16 |
SDA/DA |
|
SCK GPIO15 |
SCL/CL |
|
3.3v |
VCC/VIN/+ |
|
GND |
GND/- |
Ie change 18 and 17 to 16 and 15.
Page 334
middle of page
int n = 4252;
change to
int n = 252;
Page 340
replace
The biggest complication in using flow control with the ESP32 is that the RTS signal is linked to the Rx FIFO buffer and not the Rx ring buffer. What this means is that the ESP32 will send a signal to stop the transmission when its FIFO buffer is full, even though there might be lots of space in the ring buffer.
with
The biggest complication in using flow control with the ESP32 is that the RTS signal is linked to the Rx FIFO buffer and not the Rx ring buffer. What this means is that the ESP32 will send a signal to stop the transmission when its FIFO buffer is full, even though there might be lots of space in the ring buffer. Another complication is that data is transferred to the Rx Ring buffer, which has to be at least as big as the FIFO buffer, usually 128 bytes, and the FIFO buffer starts sending data at once. This means that the RX FIFO buffer is emptying as incoming data is trying to fill it. This means that the number of bytes it can receive before reaching the threshold is more than you might have guessed.
This is a clarification rather than an error.
Page 342
Change
nt = uart_read_bytes(UART_NUM_2, &RecData[nr],
sizeof(RecData - nr), 30 / portTICK_PERIOD_MS);
to
nt = uart_read_bytes(UART_NUM_2, &RecData[nr],
sizeof(RecData) - nr, 50 / portTICK_PERIOD_MS);
That is move the bracket.and change 30 to 50
Page 343
change
Also notice that the way that the FIFO and ring buffers interact complicates the picture. The data from the FIFO buffer is transferred to the ring buffer, which has to fill before the FIFO buffer fills and sets RTS low. The result is that the data is received in blocks of 354 bytes rather than 128 bytes. When the RX FIFO is full, defined by the 50-byte rx_flow_ctrl_thresh field, the transmission from the TX FIFO stops emptying, but it too is kept topped up from the TX ring buffer and so, as soon as the RTS line returns high, it starts sending data again. In this way all of the data is sent.
to
Also notice that the way that the FIFO and ring buffers interact complicates the picture. The data from the FIFO buffer is transferred to the ring buffer, which has to fill before the FIFO buffer fills and sets RTS low. The result is that the data is received in an initial block of 350 bytes rather than 128 bytes. When the RX FIFO is full, defined by the 50-byte rx_flow_ctrl_thresh field, the transmission from the TX FIFO stops emptying, but it too is kept topped up from the TX ring buffer and so, as soon as the RTS line returns high, it starts sending data again. In this way all of the data is sent.
That is change 354 to 350
